Nanoscale technologies, similar to other technologies, face challenges in high power consumption and signal delay due to global interconnects, but due to their scope, addressing these challenges opens new areas of research. One research area is through silicon via (TSV) based 3D integrated chip (IC) technology, where each layer or stratum is fabricated separately and subsequently vertically integrated. With 3D ICs, the fabrication of disparate strata and the final system integration may be completed in separate manufacturing facilities, allowing for greater efficiency and the possibility of modular layers. The packaging manufacturer performing the final bonding, thus, may not necessarily need each layer's technology-dependent parameters such as voltage levels and frequency of operation to assemble the 3D IC. This transparency-to-technology information allows for off-the-shelf integration where dies from different foundries are bonded together by the packaging manufacturer to form a heterogeneous 3D IC.
A semiconductor device scaling has exacerbated fundamental problems with CMOS technology like parametric variation and device aging. The most significant ill effect of these problems is seen through power supply voltage variation. Conventional microprocessor designs compensate for the worst case power supply voltage variation by introducing voltage guard bands which leads to a significant overhead on the total power consumption of the IC. In-situ aging sensors are deployed on microprocessors to automate the effects of circuit aging. However, a run-time aging detection and correction technique which can be used in tandem with on-chip voltage regulators is missing.